Free Download Cadence SSV Release Version 20.17.000-ISR7 | 41.4 Gb
The SSV Release Team has unveiled the Cadence Silicon Signoff and Verification (SSV) 20.17.000-ISR7. This solution encapsulates a set of tools that address a series of electrical and physical signoff and verification steps that designers must perform on their design before tapeout.
Product:Cadence Silicon Signoff and Verification (SSV)
Version:20.17.000-ISR7 *
Supported Architectures:x86_64
Website Home Page :www.cadence.com
Languages Supported:english
System Requirements:Linux **
Size:41.4 Gb
Featured Enhancements
Here is a list of some of the important updates made to Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution for the 20.1 production release:
Tempus
Tempus Power Integrity Solution Introduced
The Tempus Power Integrity (Tempus PI) solution integrates the Tempus and Voltus solutions to:
- perform IR-aware timing analysis and failure fixing
- reduce IR drop margins to improve power and area
- utilize proprietary vectorless-based algorithm to identify critical paths most likely impacted by IR drop
Enhanced Support for Integrated Signoff Closure
Tempus Signoff ECO now has the capability to perform DRV, Setup, Hold, and Power Optimization together in the path-based analysis (PBA) mode. This functionality is available through the Innovus cockpit. The new flow enhances user experience by providing easy-to-use Tempus ECO solution. It results in fewer iterations for improving power, performance, and area (PPA).
Supported OS and Platform Levels
This build is based on the 2019 platform support matrix, linux only. From this release onwards RH6.5 is the minimum requirement.
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